1. Technical Field
The present invention relates in general to multi-threaded processes in data processing systems utilizing low-end, commodity processors and in particular to emulation of multi-threaded processes in single-threaded operating systems through timer routine interrupts. Still more particularly, the present invention relates to emulating multi-threaded processes in single-thread, single level interrupt operating systems by configuration of a timer interrupt to switch between processes.
2. Description of the Related Art
In many contemporary microprocessor environments, such as those found in consumer electronics, automotive electronics, and industrial controllers, the operating system permits only a single-threaded process. These operating systems are inexpensive since the code for the operating system is relatively easy to implement. By definition, single-threaded processes allow execution only within a single, contiguous code body where operation is strictly sequential. The sequential operation in such an environment typically involves a short, transient flow of one-time operations followed by code looping, where the execution logic continuously polls the state of various external parameters and takes action according to the parameter values.
One problem which occurs is that the need to pursue multi-threaded operations often arises within such an environment after functionality has been developed for a single-threaded operating system. Such needs are normally dealt with either by moving to a multi-threaded operating system and rewriting code for the new operating system or rewriting the single-threaded code body to include the new functionality by recursive calls within the single-threaded limitation. Both approaches require substantial effort in the form of extensive testing to ensure that the desired functionality remains intact. This may not be warranted where the need for true multi-tasking is not required, merely the need to expand the functionality of commodity processors.
It would be desirable, therefore, to provide a system for emulating multi-threaded processes in a single-threaded operating system supporting only single level interrupts.